1. Field of the Invention
The present invention generally relates to silicon-on-insulator (SOI) semiconductor devices and, more particularly, to a structure and fabrication process which provides for more robust electrostatic discharge (ESD) protection in SOI devices.
2. Background Description
SOI complimentary metal-oxide semiconductor (CMOS) output buffers do not perform as well as "bulk" CMOS output buffers formed in the silicon substrate for either positive or negative ESD impulses. Given ESD structures are also designed in the silicon layer (e.g., they are made of diodes or SOI metal oxide field effect transistors (MOSFETs)), ESD protection, as a general rule, will not be as good as bulk devices where the heat can be dissipated to the bulk and where the film thickness is greater. In practice, SOI output buffers have been shown to have two times lower ESD robustness when compared to bulk CMOS output buffers.
In general, circuit elements which compose input/output (I/O) circuitry will demonstrate a greater sensitivity to electrical overstress (EOS), ESD, and power-to-failure compared to bulk CMOS technologies when self-heating is involved in the failure mechanism. This consists of the p-channel MOSFETs, n-channel MOSFETs, buried resistor elements, decoupling capacitors, diodes, parasitic bipolar elements, and any other features used in CMOS-on-SOI, and SOI (including silicon-on-sapphire (SOS)).
In SOI, certain ESD concepts will not work. For example, thick field oxide ESD structures are impractical. In bulk CMOS, the p+ source/drain implants, p+, n+, and well structures are used as diode elements for ESD networks. In bulk CMOS, these can be formed without the presence of the polysilicon gate structure. Standard ESD networks, such as "double-diode networks," are constructed of p+ diffusions in well tubs, and n+/n-well elements in the bulk substrate. Parasitic npn and pnp transistors are also utilized to create pnpn silicon controlled rectifiers. In thin film SOI, these structures are not constructable or available to form standard diodes, pnp transistors, npn transistors, pnpn or thick oxide elements. As SOI technologies are scaled, the film thickness above the insulating layer will decrease, hence ESD robustness will decrease with continued scaling of the SOI technology (see, Chan et al., IRPS, 1994).
It has been proposed that ESD performance can be improved by designing drivers and diode-based ESD structures in bulk silicon, (see, Chan et al., ibid.). This approach has many drawbacks. First, these structures must be built below the buried oxide layer, and this creates difficulties in terms of increased processing steps, bulk wafer contamination, and gettering concerns. Second, the fabricated device has a significantly different characteristic on input/output (I/O). Third, a non-planar structure results. Fourth, this approach negates the advantages of SOI where there is no interaction with the bulk substrate, wafer contamination is avoided, and other gettering concerns are alleviated.
As indicated above, in bulk CMOS, the p+ source/drain implants, p+, n+, and well structures are used as diode elements for ESD networks. In SOI, a diode can be created between the source/drain implants and the MOSFET body. The active area of the diode in fully depleted SOI will be the width of the diode times the film thickness. The junction area that abuts the oxide film will not be utilized in supplying diode current. As a result, creating a low resistance diode of significantly small perimeter is not practical in very thin film SOI technologies. ESD robustness and the effectiveness of a diode as an ESD network is a function of the diode series resistance. As the diode series resistance increases, the ESD robustness and effectiveness decreases. To utilize the standard scaled SOI diode as an ESD element is compromised as the film thicknesses is scaled.
In general, in SOI, a good diode element is unavailable. Non-SOI CMOS circuitry makes use of the diode element for temperature reference and phased locked loop (PLL) circuitry. An alternate solution of creating a diode by implanting the N and P dopants at opposite ends of a gate poses the difficulty that the diode characteristics will be influenced by the thickness of the active silicon layer, by the quality of the front and back gate oxides, and by the leakage characteristics of the structure.
U.S. Pat. No. 5,258,318 to Buti discloses a method of forming an SOI BiCMOS integrated circuit on a planar structure wherein the CMOS devices are formed in a thin epitaxial layer and the bipolar devices are formed in a thick epitaxial layer. Buti does not teach or suggest the formation of ESD protect circuits on the thick epitaxial layer.
U.S. Pat. No. 5,294,823 to Eklund discloses a method of forming an SOI BiCMOS circuit on a non-planar structure whereby the CMOS transistors are formed in the first, thin epitaxial layer and the bipolar transistors are formed on the composite epitaxial depositions. Eklund does not show forming ESD protect circuits in the composite epitaxial layer.
U.S. Pat. No. 4,989,057 to Lu describes a conventional n-channel SOI transistor for use as an ESD protect circuit.
Davari et al., in IBM Technical Disclosure Bulletin, Vol. 34, No.6, pp.264-5, November, 1991, discloses a method of forming a planar structure with multiple thicknesses of silicon-on-insulator for fabrication of CMOS and lateral bipolar structures.
U.S. Pat. No. 4,423,431 to Sasaki discloses an ESD device on bulk silicon or SOI wherein the ESD circuit includes an aluminum electrode on top of the PSG dielectric which integrates with the standard MOS processing. Sasaki also shows the use of a thick gate insulating layer and eliminating the standard gate electrode.